1. Field of the Invention
The invention pertains generally to semiconductor devices and, more particularly, to complementary metal oxide semiconductor devices.
2. Art Background
Complementary metal oxide semiconductor (CMOS) integrated circuit devices have come into increasing use because, among other advantageous properties, they consume relatively little power and exhibit relatively high noise immunity. CMOS devices include both n- and p-channel field effect transistors (FETs) in the same substrate. These FETs are fabricated either in a bulk region of the substrate or in a tub (or tubs) formed in the substrate--the tub and the bulk region having either significantly different effective majority carrier concentrations or different majority carrier types. One device configuration (the single-tub configuration) utilizes FETs produced both in one or more tubs having the same conductivity types and in a bulk region of opposite conductivity type. The active channel of each FET, irrespective of location, has a conductivity type opposite to that of the region in which it is fabricated. In a second device configuration (the twin-tub configuration), FETs are fabricated in two different kinds of tubs, the first kind having a conductivity type opposite to that of the second kind.
Irrespective of configuration, CMOS devices are fabricated using procedures which are generally similar. Typically, dopants are incorporated into one or more portions of a substrate surface either by dopant implantation or by diffusion from a solid or gaseous dopant source. The substrate is then heated to diffuse the incorporated dopants into the body of the substrate to form one or more tubs. During the heating process, the incorporated dopants necessarily diffuse in all directions, e.g., downwardly (in the depth direction) into the substrate and laterally (transversely to the depth direction). This diffusion process results in dopants diffusing laterally beyond the boundary of the dopant incorporated surface portion to produce an annular region encircling the core tub region. In the case of a single-tub device, the annular region constitutes a transition zone across which conductivity type changes from that of the core tub region to that of the surrounding substrate. The effective majority carrier concentration in any portion of this transition zone is lower than that of the core (in a portion having the same conductivity type as that of the core) or the substrate (in a portion having the same conductivity type as that of the substrate). In the case of a twin-tub device, the lateral diffusion of p- and n-type dopants (from their respective dopant incorporated surface portions) toward each other yields a region of commingled dopants. Because of dopant compensation, this interface region also constitutes a transition zone across which conductivity type changes from p-type to n-type, and in which the effective majority carrier concentrations are lower than those of the core tub regions.
During operation of conventionally fabricated CMOS devices, undesirable leakage currents are often produced through conductivity type inversion in regions of low majority carrier concentration, i.e., transition zones. This inversion is induced at conventional operating voltages (e.g., 0 volts or 5 volts) by fields emanating from conductors, e.g., a signal lead, crossing a transition zone. The inversion, in turn, produces conducting paths between regions of the same conductivity type that were previously isolated by the uninverted transition region, e.g., between the source/drain regions of an FET in one tub (or substrate) and the adjacent, opposite-conductivity-type tub (or surrounding substrate). To prevent such leakage currents, FET formation in transition zones is avoided, i.e., the source and drain regions of the n-channel and p-channel FETs of CMOS devices are spaced from a transition zone by at least 1 .mu.m. Because transition zones are typically 4 .mu.m or more in width, these FETs are thus separated from one another by at least 6 .mu.m, resulting in a relatively low packing density.
Providing a relatively large separation, e.g., 10 .mu.m, between the n-channel and the p-channel FETs of a CMOS device has also been viewed as necessary to prevent yet another undesirable conduction phenomenon known as latchup--a phenomenon which produces either a temporary malfunction of the CMOS device or, in some cases, permanent device damage. (Regarding latchup, and latchup-avoidance techniques, see, e.g., S. M. Sze, editor, VLSI Technology (McGraw Hill, 1983) Chapter 11).
Thus, those engaged in the development of CMOS devices have sought, thus far without success, methods for fabricating CMOS devices which avoid the formation of transition zones, and thus permit higher packing densities, without necessarily inducing unacceptable latchup.